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1 ? ISL6534 dual pwm with linear the ISL6534 is a versatile triple regulator that has two independent synchronous-rectified buck controllers with integrated 12v gate drivers (out1 and out2) and a linear controller (out3) to offer prec ision regulation of up to three voltage rails. an optional shunt regulator allows 12v only operation, when a 5v supply is not available. each controller has independent soft-start and enable functions combined on a single pin. a capacitor from each ss/en pin to ground sets the soft-start time, and pulling ss/en below 1.0v disables the controller. the ss/en pins can be controlled independently or they can be ganged together to provide complete cont rol of start-up coordination. the pgood function indicates when all regulators have completed their soft start and provides an indication of short- circuit conditions on either switching regulator. there are two ways to control the switching frequency of the pwm regulators. the default switching frequency is 300khz (fs_sync pin open). a resistor from fs_sync to ground increases the switching frequency (up to 1mhz). connecting the gate signal from another pwm ic synchronizes the ISL6534 switchers to the frequ ency of the other controller. this allows independent regulators operating at a common frequency to avoid low-frequency beats. the gate drivers for ddr mode can be staggered by 90 in order to minimize cross-conduction. switcher out1 has an internal 0.8% accurate reference for regulating any voltage down to 0.6v. out2 has current sinking capability and an external reference input allowing convenient connection to out1 through a resistor divider for ddram applications. the 3.3v reference pin provides the option for independent regulation of out2. the linear controller drives an external n-channel mosfet, making the ISL6534 one of the most versatile regulators available. simplified block diagram features two synchronous-rectified buck controllers - voltage mode control - vin range up to 12v - vout range from 0.6v to 6v - 12v lgate drivers; up to 12v boot strap for ugate switcher references - 0.6v reference for out1 (0.8% accurate) - 3.3v reference output for out2 (0.8% accurate) - external reference input for out2 - buffered vtt reference output switcher clocking - phase options for optimal clock relationship - resistor-selectable switching frequency (300khz default; resistor to ground for 300khz to 1mhz range) - synchronization-capable switching frequency (connect fs_sync to separate regulator) single linear controller - drives n-channel mosfet - 0.6v reference (0.8% accurate) - vin range up to 12v - vout range from 0.6v to 6v 12v and 5v supplies required (but optional shunt regulator can generate vcc = 5.8v from 12v) three independent soft-start/enable pins - gang together or control independently pgood output indicates all outputs available thermally enhanced qfn or tssop package qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free available (rohs compliant) boot1 ugate1 lgate1 boot2 ugate2 lgate2 ss2/en2 refin fb2 comp2 fb1 fs/sync comp1 ss3/en3 ss1/en1 out1 pwm controller out2 pwm controller out3 linear controller fb3 refout vref 3.3v drive3 pgood data sheet december 21, 2004 fn9134.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn9134.1 pinouts (see pin descriptions, page 9) ordering information part number temp. (c) package pkg. dwg. # ISL6534cv 0 to 70 24 ld eptssop (exposed pad) m24.173b ISL6534cvz (see note) 0 to 70 24 ld eptssop (exposed pad) (pb-free) m24.173b ISL6534cr 0 to 70 32 ld 5x5 qfn l32.5x5 ISL6534crz (see note) 0 to 70 32 ld 5x5 qfn (pb-free) l32.5x5 note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which ar e rohs compliant and compatible with both snpb and pb-free solder ing operations. intersil pb-free products are msl classified at pb-f ree peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std- 020c. add ?-t? suffix for tape and reel. ISL6534
3 fn9134.1 block diagram output1 drivers gate control logic dead-time control power on reset and control vcc boot1 ugate1 lgate1 ss1/en1 boot2 ugate2 lgate2 ss2/en2 vcc5 30 a vcc5 30 a vcc12 refin fb2 comp2 fb1 fs/sync clock and sawtooth generator fb3 drive3 pgnd gnd reference comp1 ss3/en3 vcc5 30 a refout 0.6v 3.3v 3.3v 5.8v 3.3v vcc5 vref 0.6v 0.6v pgood 3.3v 1-2 clock cycle filter pgood = all 3 ss ramps done with no comp short monitor comp pins for shorts if short > filter, shut down all 3 outputs bias current output2 drivers gate control logic dead-time control figure 1. block diagram ISL6534
4 fn9134.1 typical application, ddram controller note: not all components are nec essary in all applications. figure 2. typical application, ddram controller boot1 ugate1 drive3 fb3 comp1 fb1 gnd lgate1 pgnd vin1 boot2 ugate2 lgate2 vcc12 vcc12 refin vcc vcc12 refout ss1/en1 ss3/en3 ss2/en2 vref pgood vttref fs/sync vout2 vout1 ISL6534 ddr mode vin3 vcc vout1 vcc vout2 fb2 comp2 vbs1 vbs2 vcc12 vref ISL6534 vout1 ( ddr ) ddr vin2 = vout1 ( ddr ) or other optional r for shunt regulator voltage inputs required vcc12 (12v) vcc (5v or 5.8v from shunt) vin1, vbs1 vin2, vbs2 vin3 voltage outputs vout1 vout2 vout3 vout3 ISL6534
5 fn9134.1 typical applicat ion, independent mode note: not all components are necessary in all applications. figure 3. typical application, independent mode boot1 ugate1 drive3 fb3 comp1 fb1 gnd lgate1 pgnd vin1 boot2 ugate2 lgate2 vcc12 vcc12 refin vcc vcc12 refout ss1/en1 ss3/en3 ss2/en2 vref pgood vttref fs/sync vout2 vout1 ISL6534 independent mode vin3 vcc vout1 vcc vout2 fb2 comp2 vbs1 vbs2 vcc12 vref ISL6534 vref ( ind ) ind vin2 optional r for shunt regulator voltage inputs required vcc12 (12v) vcc (5v or 5.8v from shunt) vin1, vbs1 vin2, vbs2 vin3 voltage outputs vout1 vout2 vout3 vout3 ISL6534
6 fn9134.1 absolute maximum ratings thermal information supply voltage (vcc12) . . . . . . . . . . . . . . . . . gnd - 0.3v to 14.0v supply voltage (vcc, separate supply). . . . . . . gnd - 0.3v to 5.5v supply voltage (vcc, shunt regulator) . . . . . . . gnd - 0.3v to 6.0v ugate1, ugate2, boot1, boot2 . . . . . . . . . . gnd - 0.3v to 30v lgate1, lgate2, drive3 . . . . . . . . . . . . . . gnd - 0.3v to vcc12 fs_sync (through 10k resistor). . . . . . . . . . . . . gnd - 0.3v to 12v refin, refout, pgood, vref . . . . . . . . . . . gnd - 0.3v to vcc fb1, comp1, fb2, comp2, fb3 . . . . . . . . . . . gnd - 0.3v to vcc ss1/en1, ss2/en2, ss3/en3. . . . . . . . . . . . . . gnd - 0.3v to vcc pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to gnd + 0.3v esd rating human body model (per mil-std-883 method 3015.7) . . .1500v machine model (per eiaj ed-4701 method c-111). . . . . . . .100v charged device model (per eos/esd ds5.3, 4/14/93) . . .1000v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to 70c vcc12 supply voltage range (typical) . . . . . . . . . . . . . 12v 1.2v vcc supply voltage range (typical) . . . . . . . . . . . . . . . . 5v 0.5v vcc shunt regulator voltage range (typical) . . . . . . . 5.8v 0.2v thermal resistance ja (c/w) jc (c/w) eptssop package (notes 1, 2) . . . . . 37 4 qfn package (notes 1, 2) . . . . . . . . . . 32 4 maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___w maximum junction temperature (hermetic package or die) . . . 175c maximum junction temperature (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v cc = 5v, v cc12 = 12v, t a = 0c to 70c, unless otherwise specified parameter test conditions min typ max units input supply power input supply current (quiesc ent) vcc; outputs disabled 4 ma vcc12; outputs disabled 6 ma input supply current (dynamic) vcc12; ugates, lgates cl = 1nf, 300khz 50 ma vcc; ugates, lgates cl = 1nf, 300khz 7 ma shunt regulator output voltage 40ma current; ~equivalent to 150 ? resistor vcc to 12v 5.6 5.8 6.0 v shunt regulator current 150 ? resistor vcc to 12v 40 ma power-on reset threshold vcc rising 4.15 4.23 4.4 v vcc falling 3.9 4.0 4.15 v vcc12 rising 7.8 v vcc12 falling 7.3 v system accuracy outputs 1 and 3 reference voltage 0.6 v output 2 reference voltage 3.3v outputs 1 and 2 system accuracy (note 3) -0.8 0.8 % output 3 system accuracy (note 3) -0.8 0.8 % oscillator accuracy -20 20 % frequency fs_sync pin open 240 300 360 khz ISL6534
7 fn9134.1 adjustment range fs_sync pin: resistor to gnd; see figure 12 for curves 300 1000 khz sawtooth amplitude 2.1 v duty-cycle range 0 87.5 % error amplifier (out1 and out2) open-loop gain rl = 10k ? to ground; (note 5) 85 db open-loop bandwidth cl = 100pf, rl = 10k ? to ground; (note 5) 15 mhz slew rate cl = 100pf, rl = 10k ? to ground; (note 5) 4 v/s ea offset comp1/2 to fb1/2; compare to internal vref/refin 2 mv maximum output voltage rl = 10k ? to ground; (may trip short-circuit) 3.6 4.1 v output high source current comp1/2 -8 ma output low sink current comp1/2 6 ma protection and monitor under-voltage threshold (comp1 and comp2) causes pgood to go low; if there for a filter time, implies the comp pin(s) is out -of-range, and shuts down ic 3.3 v uv filter time based on inte rnal oscillator clock frequency (nominal 300khz = 3.3s clock period) 12clock pulses pgood low voltage ipgood = 2ma 0.1 0.3 v linear regulator (out3) output voltage (as determined by re sistor divider into fb3) 0.6 3.3 v ea offset drive3 to fb3; compare to internal vref 2 mv drive3 high output voltage 9v drive3 high output source current 0.4 ma drive3 low output sink current 0.4 ma vref output voltage 1.1f max capacitance 3.3 v output accuracy -0.8 +0.8 % source current 2.0 ma refout (vttref) output voltage determined by refin voltage 0.6 3.3 v offset voltage -10 +10 mv source current 0.2 20 ma sink current 0.48 ma output capacitance 0.4 2.2 f output high voltage minimum to select 0 degree phase; see table 1 4.7 vcc v enable/softstart (ss/en 1, 2, 3) enable threshold en rising 1.05 v en falling 0.95 noise immunity (noise de-glitch) 6s soft-start current -30 a electrical specifications operating conditions: v cc = 5v, v cc12 = 12v, t a = 0c to 70c, unless otherwise specified (continued) parameter test conditions min typ max units ISL6534
8 fn9134.1 soft-start high voltage end of ramp 3.3v v output high voltage to select ddr mode; see table 1 4.7 vcc v fs/sync pll frequency range of lock-in 350 850 khz high voltage use a 10k series resistor (from lg pin of another ic, for example) 12 v boot pins (boot1, 2) high voltage voltage with respect to gnd; also depends upon vin, phase, vout, and threshold of nfet 830v gate drivers output high source current ugate1, ugate2 1.5 a output high source current lgate1, lgate2 1.5 a output low sink current ugate1, ugate2 1.5 a output low sink current ugate1, ugate2 1.5 a output voltage ugate1, ugate2 30 v output voltage lgate1, lgate2 12 v upper driver source resistance ugate1, ugate2 = 3v; boot = 12v 2 ? lower driver source resist ance lgate1, lgate2 = 3v 2 ? upper driver sink resistance ugate 1, ugate2 = 3v; boot = 12v 2.8 ? lower driver sink resistance lgate1, lgate2 = 3v 2.8 ? gate drivers switching time ugate rise time 10% - 90%; 2nf load; boot = 12v 17 ns ugate fall time 90% - 10%; 2nf load; boot = 12v 17 ns ugate rise time 10% - 90%; 2nf load; boot = 24v 27 ns ugate fall time 90% - 10%; 2nf load; boot = 24v 25 ns lgate rise time 10% - 90%; 2nf load 17 ns lgate fall time 90% - 10%; 2nf load 17 ns notes: 3. operating range is: 12v 10%; 5v 10%. 4. thermal comments. 5. guaranteed by design. electrical specifications operating conditions: v cc = 5v, v cc12 = 12v, t a = 0c to 70c, unless otherwise specified (continued) parameter test conditions min typ max units ISL6534
9 fn9134.1 vcc this power pin supplies bias to the control functions. it can be connected to a nominal 5v (10%) supply, or it can function as a shunt regulator (nominal 5.8v), with an external pull-up resistor (nominally 150 ? to 12v). gnd this pin is the signal ground for the ic. the metal thermal pad under both packages is connected to the gnd potential (through the ic substrate; the pad does not substitute for the gnd pin connection). but the gnd pin and the metal pad should be connected together on the board, and tied to a good gnd plane (both for electrical and thermal conduction). note that the thermal pad on both packages limits metal interconnect traces underneath the package. vcc12 (qfn: vcc12_1, vcc12_2) this power pin (nominal 12v) supplies the output gate drivers, as well as some other control functions. the qfn package has two power pins; one for each switcher. they are electrically connected internally, but allow for separate decoupling caps to better isolate the switching noise, if necessary. even if they share one capacitor, they should both be connected externally, for lower resistance. pgnd (qfn: pgnd_1, pgnd_2) this pin is the power gnd for the gate drive circuits. it is not directly tied to gnd inside the ic; it should be tied to gnd on the board. the qfn package has two power gnds; one local to each switcher; both should be connected externally to the gnd plane on the board. ss1/en1, ss2/en2, ss3/en3 these analog input pins have two functions. a 30a current source charges an external capacitor (to gnd), to provide a soft-start timing ramp; their respective output voltage will follow the ramp voltage as it powers up. the 2nd function is enable; when the input is left open (with the soft-start cap), the respective output will be enabled after the ramp reaches the 1v level. if the input is pulled to a low logic level, the output will be disabled. ss2/en2 also has a special mode function; see table 1. tying it to vcc (5v) selects the ddr mode (where both out1 and out2 share the ss1 ramp); otherwise it will be in the independent mode. comp1, comp2 these analog output pins are used to externally compensate the error amplifiers for their respective regulators. pin description 24-pin tssop top view 32 ld 5x5 qfn top view notes: 6. boot2 and ugate2 are different order in qfn. 7. nc is no connect fb1 comp1 comp2 fb2 refin ss2/en2 boot2 vcc12 fs_sync lgate2 pgnd ss3/en3 pgood ss1/en1 lgate1 vref refout ugate2 gnd drive3 fb3 ugate1 boot1 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 gnd bottom side pad nc refin nc refout fs_sync nc pgnd_2 lgate2 gnd pgnd_1 ugate2 boot1 ugate1 lgate1 boot2 comp1 vref fb3 drive3 fb2 ss2/en2 ss1/en1 nc ss3/en3 pgood vcc12_1 nc nc fb1 comp2 vcc vcc12_2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 gnd bottom side pad fb2 ISL6534
10 fn9134.1 fb1, fb2, fb3 these analog input pins are used to set their respective regulator output voltages. a resi stor divider from the output to gnd is compared to a reference voltage (0.6v for out1 and out3; refin pin for out2). the compensation components also connect to these pins. ugate1, ugate2 these output pins provide the gate drive for the upper mosfets of out1 and out2 respectively; the voltage comes from its bootstrap pin, typically 12v (minus the diode drop) above the vcc12 pin. lgate1, lgate2 these output pins provide the gate drive for the lower mosfets of out1 and out2 respectively; the voltage comes from vcc12. boot1, boot2 these pins feed the bootstrap voltage (externally generated with a diode and a capacitor) to the upper mosfets, through the ugate pins. either boot pin can be connected directly to a power supply instead (but only if the vin voltage of the regulator is sufficiently lower than that supply, such that the fets have enough gate-source voltage). refin this analog input is used as the reference voltage for out2 (the error amplifier compares it to the feedback resistor divider). this voltage is also fed into a buffer, which is output on the refout pin. refout (vtt buffer) this analog output provides a buffered version of the refin input, to be used by other ic ?s in the system. in the ddr mode, where vtt is generated from vddq, this output can be used as a vtt buffer. in addition, it can be used to select the phase relationship, but it disables the buffer in that case (see table 1). tying it to vcc (5v) selects 0 degrees phase (in either mode); leaving it open (where it can also be used as a reference output) selects 90 degrees phase (in ddr mode) and 180 degrees phase (in independent mode). a capacitor to gnd is recommended for stability (see application considerations). vref this analog output pin is a 3.3v reference, which can be used by this ic (or others) as a voltage reference. a capacitor to gnd is recommended for stability (see application considerations). drive3 this pin drives the gate of an external n-channel mosfet, for out3, which is a linear regulator. pgood this digital output is an open-drain pull-down device. when power is first applied to the ic, the output is pulled low, for power ?not good?. after all 3 so ft-start pins complete their ramp up with no faults (no shor t detected on switchers) the power is considered ?good?, and the output pin is high- impedance (to be pulled up to a logic high level with an external pull-up resistor). see the pgood section under functional description for more details. fs/sync this input allows the user to adjust the internal oscillator used for the pwm outputs; a pull-down resistor will speed up the oscillator. in addition, a digital clock signal can be fed into this input, in order to sync its clock with the external one; this allows the clock edges to line up in a way that won?t interfere with each. pinout note: note that the pin order of ugate2 and boot2 are different in the two packages, due to bonding optimization. the qfn package also adds an extra vcc12 and pgnd pin, and has additional no connection pins. functional description overview there are two single-phase synchronous buck converters, and one linear regulator. except for a common clock, the two pwm regulators are independent. refer to figures 2 and 3 for a quick discussion of the circuit. the right side of the diagram shows the 3 output stages with their components; each switcher has an upper and lower fet, input capacitor, bootstrap diode and capacitor, an lc output filter, and an optional snubber. the 3rd regulator (out3) is a linear, with an external nfet, input and output capacitor. the output voltage is divided to fb3, and compared to an internal 0.6v reference. an rc is used for compensation. the left side of the diagrams show the various control and programming components. each switcher has a compensation network for stability that includes the output resistor divider. vref and refout can be used as reference voltages. there are three ss/en pins to set the so ft-start ramp of each output, and a pgood output to signal when they are all done. the fs_sync pin allows options for the oscillator frequency. each of these features will be described in more detail, either in the functional description or the application considerations. the first regulator (out1) has an internal 0.6v reference. to set the output voltage level, connect a resistor divider between vout1 and fb1. the second regulator (out2) requires an external reference connected to refin. for ddr memory applications (figure 2), connect a divide-by-two resistor divider from vout1 to ground with the center point connected to refin. ISL6534
11 fn9134.1 this causes vout2 to track vout1 at one-half its value. connect vout2 to fb2 (through the compensation resistor). a buffered copy of refin is provided on refout. for independent mode operation on out2 (figure 3), a 3.3v reference is provided on vref which can be used directly, or divided down for refin. a resistor divider from vout2 to fb2 sets the output voltage. operational modes table 1 shows how to select the various modes and phasing between the two switching regulators. ddr mode is chosen by connecting the ss2/en2 pin to vcc (5v). in this mode, ss1/en1 is used to enable and soft- start both out1 and out2 (note that only a single 30a current source is charging a si ngle soft-start capacitor). in addition, vout1 (usually divided by 2) can be used as the refin for out2. vout1 is often used as vin2 (especially when the vout2 current is low enough) although it is not necessary. and out2 does allow both sinking and sourcing of current for the ddr. for independent mode, ss2/en2 is not connected to vcc. instead it is connected to a soft-start capacitor to gnd, similar to ss1/en1. the capacitors will ramp each output independently, and each can be turned off by pulling its ss/en pin to gnd; releasing will start a new soft-start ramp. ss3/en3 is also independent of the first two. as explained earlier, one capacitor can be shared by more than one ss/en pin. to select the phase shift between channel 1 and 2, the refout pin is used. tie it to the vcc pin to get 0 degrees in either mode (which means both switchers are in phase). in this case, the refout pin is not available for use elsewhere; the buffer is disabled. leave refout open (driven to whatever voltage is supplied at refin) and it selects 90 degrees in the ddr mode, or 180 degrees in independent mode; refout can be used as a reference in this case. the advantage of phase shift is to keep the switching current spikes from lining up to create even higher noise, or interaction between the channels; it also reduces the rms current through the input capacitors, allowing fewer caps to be employed. however, depending on the vout to vin ratios of both, there is no guarantee that opposite edges might not line up, depending on the duty cycles; so the user should check for that possibility. figure 4 shows the phases. the rising edge of lgate1 (lg1) and lgate2 (lg2) is fixed; the phase difference is relative to the rising edges. the falling edge of each is the variable one (determined by the duty cycle). lg1 is shown with a pulse width shorter than lg2; this is just an arbitrary example, and it does not affect the rising edges. output regulation the basic pwm regulator voltage is usually set up as follows: fb and the internal reference are the two inputs to the error amplifier, which are forced to be equal. the output voltage is externally divided down to the fb pin, to equal the reference. in the ISL6534, vout1 uses an internal 0.6v reference; vout2 uses an external refin pin for the reference. there are many variations of the above, especially when the modes (independent or ddr) are also considered. below are some of the cases that can be used, along with the advantages or disadvantages of each. the following figures show the compensation circuit for vout1 and vout2; they include a full type 3 compensation network. also shown is the resistor divider for refin. several notes: 1. the labeling of the resi stors may not match other diagrams; they should be used just for the equations included. 2. the vref pin (nominal 3.3v) is assumed here, but any other appropriate fixed voltage reference can be used as refin for out2. 3. one percent (or better) resistors are typically used for these resistor dividers; the overall system accuracy depends directly upon them. exact ratios are not always possible, due to the limited values of standard resistors available; these errors must also be added to the tolerance. table 1. mode and phase selection mode en_ss2 refout pwm1/2 ch1/2 ddr vcc vcc 0 deg en1/ss1 enables ch1 and ch2 ddr vcc open 90 deg ? independent ss2 cap vcc 0 deg en1/ss1 for ch1; en2/ss2 for ch2 independent ss2 cap open 180 deg ? figure 4. phase of lg2 with respect to rising edge of lg1 lg1 lg2 (0 deg) lg2 (90 deg) lg2 (180 deg) 0 90 180 270 0 ISL6534
12 fn9134.1 vout1 (independent or ddr mode) figure 5 shows the resistors for vout1. case 1 is the usual case, where r5 and r6 divide vout1 down to match the 0.6v internal reference. vout1 must be greater than 0.6v; 2 resistors are needed, and their accuracy directly affect the regulator tolerance. case 2 can be used only if vout1 equals exactly 0.6v; then no divider is needed; only one resistor (r5, which is part of the compensation) is needed, and its accuracy does not directly affect the output tolerance. vout1 cannot be less than 0.6v. case 1 (divide vout1): ref = 0.6v fb1 = vout1*r6/(r5+r6) case 2 (no dividers): ref = 0.6v fb1 = vout1 (no r6) vout2 (independent mode) figure 6 shows the resistors for vout2. case 1 is the most general case (no restriction on vref > or < vout2), and the most flexible. both vref and the output are divided down to the same arbitrary reference (in the 0.6v to 3.3v range for best performance). the advantage is that if either the vref or desired output voltage changes going forward, the only board change needed is the value of 1 or more resistors. the disadvantage is that since there are two resistor dividers, both of them add to the error budget of the regulator output. the total number of resistors used is 4. case 2 can be used when vout2 is less than vref. r3 and r4 divide the reference to match vout2. it saves a resistor (r2); r1 (usually ~1k ? ) is still needed as part of the compensation, but it doesn?t affect the accuracy of the output. three resistors are needed; this is the most typical case. case 3 can be used only when vout2 is greater than vref, which is brought directly into refin; then vout2 is divided down to match it. only two resistors (r1, r2) are needed, and both affect the accuracy. case 4 can be used only if vref = vout2; this case is the most accurate (since neither has a divider), and only uses one resistor (r1, as part of the compensation). case 1 (divide both signals): refin = vref*r4/(r3+r4) fb2 = vout2*r2/(r1+r2) case 2 (divide vref): refin = vref*r4/(r3+r4) fb2 = vout2 (no r2) case 3 (divide vout2): refin = vref (no r3, r4) fb2 = vout2*r2/(r1+r2) case 4 (no dividers) refin = vref (no r3, r4) fb2 = vout2 (no r2) vout2 (ddr mode) the main difference for ddr mode is that rather than using a fixed external reference for refin, a reference based on vout1 (which is also called vddq for ddr) is used instead. see figure 6. case 1 is again the most general case; both vout1 and the vout2 output are divided down to the same arbitrary reference (in the 0.6v to 3.3v range for best performance). the trade-offs are the same as case 1 for independent mode described earlier. case 2 can be used when vout2 is less than vout1, which is the case for ddr (since vout2 = 1/2 vout1). it saves a resistor (r2); r1 is still needed as part of the compensation, but it doesn?t affect the accuracy of the output. r3 and r4 divide the vout1 by 2 to match vout2. three resistors are needed, two of which affect the accuracy. since the ddr mode almost always uses the divide by two, no flexibility is lost here; just change the vout1 resistor divider to change vddq, and vout2 will still track at 1/2 the value. figure 5. resistor divider for vout1 (ddr or independent mode) comp1 fb1 vout1 r6 r5 ea 0.6v figure 6. resistor dividers for vout2 and refin vout2 comp2 fb2 r2 r1 r4 vref (ind) r3 vout1 (ddr) or ea refin ISL6534
13 fn9134.1 cases 3 and 4 don?t apply for ddr. case 1 (divide both signals): refin = vout1*r4/(r3+r4) fb2 = vout2*r2/(r1+r2) case 2 (divide vout1): refin = vout1*r4/(r3+r4) fb2 = vout2 (no r2) soft-start/enable numerous combinations of independent and dependent startup are possible by the various methods of connecting the three en/ss pins; some combinations are shown in figures 7 and 8. in figure 7, the three regulators enable independently and rise at rates selected by their individual soft-start capacitors c ss1 , c ss2 , and c ss3 . in figure 8, two diodes are used to connect to a single open-drain pull-down device (not shown); this allows one fet to disable both channels. when enabled, they will each rise at their own ramp rate. if they could use the same ramp rate, then both pins could share one capacitor and the one fet, and the diodes are not necessary. the 3rd channel is disabled and ramped independently. note that since the en trip point is around 1v, some care should be taken to guarantee the diode drop and the fet in series with it will always be below it. the soft-start pins can share the same capacitor, to ramp them all at the same rate (but since there will be 3 times the current, the value of the capacitor needs to be approximately 3 times bigger, for the same ramp rate). note that each output rise do es not start until its ss/en voltage reaches ~1v; the output will then start to ramp up until the soft-start is > ~3.3 v (ramp is done). pgood will not go active unless all three ramps are >3.3v (and no faults are detected). figure 9 shows the start-up waveform for vout1 at power up. in this example, the vcc voltage is generated from the internal shunt regulator. the ramp of the 12v is controlled by the external power supply; it can vary widely, depending upon the type and model used. the ramp of the shunt more or less follows the vcc12 until it reaches its regulation point at ~5.8v. both vcc and vcc12 must be past their rising por trip points before ss1 starts rising. the order doesn?t matter, and may be different, especially when the vcc uses an independent supply. when ss1 reaches ~1v, the outp ut starts up (the switching noise becomes apparent then). note that if vin1 is tied to a supply other than either vcc or vcc12, then it must be up above the desired output voltage (or at least ramping there ahead of the output) before t he ss/en1 reaches ~1v. if not, the short-circuit protection will trigger, and shut down all three outputs, requiring a por on either vcc or vcc12 to restart. if either vcc or vcc 12 is used as vin, then the voltage levels should be sufficient, as long as the design can function at the por levels, since both must hit their por levels before starting up. so, for example, if the vcc12 supply was also used as vin, then as long as the output could start up at vin = ~8v (the vcc12 rising por trip point) the start-up condition is satisfied. pgood the open-drain pull-down device is on when power is first applied to the ic, forcing the pin to a logic low, for power ?not figure 7. connections for independent enable and soft-start ss1/en1 ss2/en2 ss3/en3 c ss1 c ss2 c ss3 en3 en2 en1 open-drain logic signals ISL6534 ss1/en1 ss2/en2 ss3/en3 c ss1 c ss2 c ss3 en3 en1, 2 open-drain logic signals ISL6534 figure 8. 1 and 2 enabled together but have independent soft-starts. 3 is fully independent. figure 9. startup (vcc12, vcc, ss1/en1, vout1) 4: vcc12 3: vcc 1: vout1 2: ss1/en1 vcc12 ~8v ss1 ~1v ISL6534
14 fn9134.1 good?. after all 3 soft-start pins complete their ramp up with no faults (no short detected on ei ther switcher), the power is considered ?good?, and the out put pin goes high-impedance (to be pulled up to a logic high level with an external pull-up resistor). figure 10 shows a ddr example, with a fast ss1, a slower ss3, vout3 and t he pgood output. the pgood waits for the last of the ss sign als (ss3 here) to reach their ramp-done trip point before it goes high. note that if any of the ss/en pins is held low, pgood will not go high; thus, if one of the three outputs is not used, and the pgood function is desired, then the ss/en should be allowed to charge high, and the other pins of the unused regulator should be tied so as not to cause a fault or shutdown. options for out1 include: tying fb1 to comp1, or tying fb1 to vcc, and leaving comp1 open. vout2 is a little more difficult; tie refin, fb2, comp2 to gnd; or tie fb2 to comp2, and tie refin to a voltage well under 3v (to avoid the short-circuit shutdown). in all of these cases, leave the lgate and ugate pins open; tie boot pin to vcc12. once the power is ?good?, pgood will pull low if any of the 3 ss/en pins is pulled low. also, if a short is detected on either switcher, then the pgood will pull low, for as long as the condition is there. note that if out1 or out2 has a short detected which stays there for 1-2 clock pulses, all three regulators will shut down, and wait for a power-down and up cycle to reset (either vcc or vcc12 (or both) must power down and up). if the short-circuit is not there long enough to shut down, it may still cause pgood to go low momentarily. if this causes a system issue, a filter capacitor could be tried; it should be at least several nf to be effective. note that this is not a full-feat ure pgood; it is not directly monitoring if the vout1 or vout2 drops below a set uv level; it only checks for the si mple short-circuit condition, via the comp pins. and it is not moni toring vout3 at all. so it is a good indication that all three outputs have ramped up, but it is less useful as a monitor from that point on. since pgood is an open-drain pull-down device, it usually requires an external pull-up resistor; however, if the pin is not used, no resistor is necessary. a value in the range of 1k ? to 10k ? is typical. por both the vcc (5v) and vcc12 (12v) are monitored for power-on-reset, as shown in the specification table. the two por outputs are logically gated together, such that both have to be above their rising trip points to enable the ss/en ramps to start (if they are not held low) and then enable each output. either por output can go below its falling trip point to disable all outputs, and then back to restart the enable operation. shunt regulator the ISL6534 must have both a 12v (for vcc12) and a 5v power supply (for vcc); both must be above their respective por rising trip points to enable the outputs to start switching. the shunt regulator (nominal 5.8v) was designed for those systems that do not have a 5v supply available; the range of the shunt (5.6v to 6.0v) was designed not to overlap the usual 4.5v to 5.5v range of typical power supplies. an external resistor between vcc12 and vcc is required; a typical value of 150 ? is the recommended starting value (it may change due to other factors, such as vcc12 voltage, vbs voltages, oscillator frequency, etc.). note that the dissipation of the resistor is approximately 1/4w; it needs to be sized accordingly. for example, 12v - 5.8v = 6.2v across the 150 ? resistor is 41ma; p = iv = 0.256w. several low-power resistors in parallel can also be used. see figure 11. note that in either case, both vcc and vcc12 pins have small decoupling capacitors (typically 1.0 to 10.0f); they should each be located near th eir pin, with a via to the gnd plane. figure 10. ss1, ss3, vout3, pgood 4: pgood 1: ss1/en1 2: ss3/en3 3: vout3 (ddr mode; ss2/en2 = 5v) figure 11. shunt regulator and decoupling capacitors for vcc and vcc12 pins (vcc) = 5.8v vcc12 vcc pin vcc12 pin optional r for shunt regulator; vcc = 5.8v vcc vcc12 vcc pin vcc12 pin non-shunt mode; separate 5v and 12v ISL6534
15 fn9134.1 short-circuit protection there is no current sensing or r ds(on) sensing or under- voltage sensing on the ISL6534. however, if either channel 1 or 2 output is shorted while active, there is a simple detection on the error amp comp output that implies either over-current or under-voltage; the pgood pin goes low immediately. if the condition persists for 1-2 internal clock cycles (3-6s at 300khz), then all 3 outputs are latched off, requiring either a vcc or vcc12 por to restart. the protection was not designed to work for the case of powering up an output into a short-circ uit, and there are limitations on detecting applied shorts. note that the linear regulator has no short-circuit protection. see application considerations for more details. oscillator the internal oscillator is nominally 300khz (20% tolerance) with no external components requ ired, as measured at either of the lg or ug pins. to run faster, a resistor from fs_sync pin to gnd will speed up the frequency. see figure 12 for a curve that shows the frequency versus resistor value. note that the curve is steep as it approaches 300khz; operation in this area is not recommended. since this pin has several functions muxed onto it, it is important that they do not interfere with each other. thus, the circuit that looks for the resistor will shut off (and defaul t to the 300khz) if it doesn?t see a current in the expected ra nge. there should not be any excessive capacitive loading on the pin either, and if a resistor is used, it should be located very close to the fs_sync pin. sync with multiple switching regulators running on the same board at similar, but independent frequencies, there may be interference between them; a ?beat? frequency can develop, based on the difference between the two frequencies. to avoid this situation, the ISL6534 has a synchronization circuit that will read an external frequency, and make the ISL6534 follow it. the typical circuit involves taking the lg (lower gate) signal from another regulator, going through a series 10k ? resistor (to limit the current), and connecting to the fs_sync pin (with no other resistors attached). within a few internal clock cycles, the ISL6534 will lock-in to the new frequency, and run normally as if it were programmed to run there. if the signal is lost for any reason, after a set number of clock cycles, the ISL6534 will go back to its default internal frequency. note: do not use the oscillator of another regulator directly, since the ISL6534 will scale it up by 4 to match its own internal oscillator; using the lgate signal will allow the ISL6534 to match its lgate to the same frequency. see figure 13. note that the sync circuit expects to see a stable frequency, and can be fooled by variations. for example, if the gate signal used has both leading and falling edge modulation, or an extreme duty cycle, that might cause some confusion. skipping clock cycles completely may also be misinterpreted as a much longer period. the sync circuit was designed to work over a range of 350khz to 850khz. application considerations decoupling capacitors both the vcc12 and vcc pins should have a decoupling ceramic capacitor (typical values are 1 - 10f), located as near to the pin as possible, and with the gnd connection as a via to a wide gnd plane. a low-value resistor in series with the capacitor may help isolate the switching noise from the power supply from affecting the capacitor, especially if either pin is sharing a power supply with other noisy circuits (but adding a resistor in series with the shunt regulator resistor gives no advantage). figure 12. typical clock period vs fs_sync resistor to gnd 400 350 300 250 200 150 100 50 0 r (k ? ) 1 1.5 2 2.5 3 3.5 period (s) figure 13. connection of fs_sync to the lgate of another switching regulator vin1 ugate1 lgate1 vout1 rfs fs_sync ISL6534 other regulator ISL6534
16 fn9134.1 ss_en capacitors the basic formula for the soft-start is: plugging in the known values, and adjusting units, time (in ms) = 110 * c (in f). so, for example, a 0.1f capacitor will give a ramp time of 11ms, and a 1.0f capacitor will give a ramp time of 110ms, which is around the practical maximum value allowed, before noise and leakage and other factors start changing the formula. faster ramps are allowed, as long as the input supplies are capable of charging the output capacitors (and possibly the load currents, if present at power-up), without drooping too mu ch (for example, if either the 5v or 12v supply is dragged down below its por falling trip point, because of output loading, that might imply that the output ramp is too fast (or perhaps bigger input capacitors are needed, or poss ibly other explanations as well). note that the above formula determines how long the soft- start ramp time is. but since the outputs don?t turn on until the ss/en pin reaches ~1v, that means the actual time the output ramps is only ~70% of the total ss ramp. note that each of the three regulators can have its own independent ramp rate, as well as their own independent enable function (pulling one of the ss_en pins below 1v nominal will shut down that out put). two or three pins can be tied together to share a comm on ramp and enable; but note that there are now two or three times the current charging a single cap, so the formula should be adjusted accordingly. if you need the same ramp rate, but separate enable functions, then don?t share the capacitor; just use the same value capacitor on each, which will still allow independent enabling. if you need different ramp rates, but want to share a single enable signal, you will probably need to connect a separate pull-down fet to each pin, and just drive their gates from a common signal, or use diodes to isolate a single fet to multiple pins (as previously shown in figures 7 and 8). vref/refout capacitors the vref output may require a small capacitor to gnd to remain stable; 1.0f is recomm ended. if the output is not used (for example, in ddr mode, where if vout1 is divided down for refin); it could be left open, but the additional noise and current draw may be objectionable. so even then, a capacitor is recommended. the refout output is sim ilar; a 0.1f capacitor is recommended. if the output is not used, it could be left open, but the additional noise and current draw may be objectionable. so even then, a capacitor is recommended. linear (vout3) component selection once the vin3 and vout3 levels are defined, the nfet is chosen to handle the output load current and the power dissipation it creates. the power is determined by: even if the fet is in a good thermal package (such as a d-pak), the mounting of the fet will determine how much power dissipation is allowed. if simply placed on a pad on an fr4 board, the dissipation will be limited by the area of the pad; the more area, the lower the temperature will be. the recommendation is to use large plane areas, as well as thermal vias to the back of the board, plus additional area there, if possible. even then, power dissipation is usually limited to 1w or so, which would give 1a (assuming a 1v drop from vin3 to vout3). see figure 14. the output capacitor c out3 should be chosen for output filtering and transient response needs. however, the output capacitor also affects the stabi lity of the regulator, so the choice is limited to a range of acceptable values, which include the capacitance and its esr (effective series resistance). the input capacitance c in3 is chosen to keep the input supply from changing too much when the output current load changes; this is related to transient response. the resistor ratio is chosen to divide the desired output voltage down to make the fb3 pin = 0.6v. a typical value of 1k ? for the combined resistance is a good starting value. the full equation is vout3* (r2/(r1+r2) = fb3 = 0.6v. compensation components r3 and c3 are chosen to make the output stable under the c onditions being used. choose the values to add a zero around 30khz to cancel a pole. values of 4.75k and 6800pf are a good starting point. note: if the linear output is not used, leave ss/en3 open (or tie to ss1 or ss2); and tie drive3 to fb3, with no other components; this should disable vout3, but keep pgood active for vout1 and vout2. tc dv i ------- ? = where t is the soft-start ramp time c is the external capacitor to gnd on the ss pin dv is the voltage the ramp charges up to (nominal value is 3.3v) i is the charging current (nominal 30a). time (in ms) = 110 * c (in f). or: power vin3 vout3 ? () iload ? = figure 14. linear (vout3) regulator component selection drive3 fb3 vin3 cout3 r3 r1 r2 c3 cin3 vout3 ISL6534
17 fn9134.1 connecting one input from another output often, one of the 3 outputs g enerated is used as the input voltage to a 2nd (and perhaps 3rd); the general case includes input or outputs of other ic regulators as well. this can be done, with a few precautions in mind. 1. the first output must be designed and sized for its own load current, plus the expected input current of the other channels. 2. the sequencing of the output s must be consistent. the first output cannot be disabled or have a much slower ss/en ramp than the input channel, in order to take full advantage of the soft-start. if the vin is not present when the 2nd regulator tries to start up, that can be interpreted as a short-circuit, and the whole ic could be shut down. 3. the output capacitor of the first is now also the input capacitor of the 2nd, so it needs to be chosen and sized for both conditions. for example, transients on the first output show up on the input of the 2nd; and input current transients on the 2nd can affect the output of the first. there may also be trade-offs of the placement of the various capacitors; some might be near the output fets of the first, and some near the input fets of the 2nd. 4. the linear regulator has no short-circuit protection. however, if vin3 is connected to one of the switcher outputs, a short on the linear output may be detected; but it is subject to all the cautions mentioned in the short- circuit protection section. feedback compensation the compensation required for vout1 and vout2 is similar to many other switching regulators, and the same tools can be used to determine their component values. note that vout1 and vout2 are simi lar with respect to the compensation; the only difference is their reference voltages (fixed 0.6v versus refin, whic h does not directly affect the component values). the schematics show type 3 compensation, but the simpler type 2 is also possible, under the right conditions. it is recommended to have footprints for the type 3, in case it is ever needed; the type 2 is a subset of that. a simple rule of thumb is that when bulk capacitors are used on the outputs, the esr is often high enough (10?s - 100m ?) to use type 2 compensation. but if only ceramic capacitors (esr ~ 1?s m ?) are used on the outputs, then most likely type 3 will be required. note that the component labels match the equations given in this section, but may not match other diagrams in this datasheet. figure 15 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (vout) is regulated to the reference voltage level. the error amplifier (error amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated (pwm) wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). the modulator transfer function is the small-signal transfer function of vout/v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to-peak oscillator voltage ? v osc . modulator break frequency equations the compensation network consists of the error amplifier (internal to the ISL6534) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180 o . the equations below relate the compensation network?s poles, zeros and gain to the components (r1, r2, r3, c1, c2, and c3) in figure 15. note again that the component names from figure 15 apply to the equations below; they may be labeled with different names elsewhere in this document. use these guidelines for locating the poles and zeros of the compensation network: v out osc reference l o c o esr v in ? v osc error amp pwm driver (parasitic) - ref r1 r3 r2 c3 c2 c1 comp v out fb z fb ISL6534 z in comparator driver detailed compensation components phase v e/a + - + - z in z fb + figure 15. voltage-mode buck converter compensation design f lc 1 2 l o c o ? ? -------------------------------------- - = f esr 1 2 esr c o ? () ? -------------------------------------------- - = ISL6534
18 fn9134.1 compensation break frequency equations 1. pick gain (r2/r1) for desired converter bandwidth 2. place 1 st zero below filter?s double pole (~75% f lc ) 3. place 2 nd zero at filter?s double pole 4. place 1 st pole at the esr zero 5. place 2 nd pole at half the switching frequency 6. check gain against error amplifier?s open-loop gain 7. estimate phase margin - repeat if necessary figure 16 shows an asympt otic plot of the dc-dc converter?s gain vs. frequency. the actual modulator gain has a high gain peak do to the high q factor of the output filter and is not shown in figure 16. using the above guidelines should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the erro r amplifier. the closed loop gain is constructed on the log-log graph of figure 16 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing with - 20db/decade slope and a phase margin greater than 45 o . include worst case component variations when determining phase margin. fet selection (vout1, vout2) the typical fet expected to be used will have a low r ds(on) (5-10m ? ) and a low vgs (gate-to-source threshold voltage; 1-2v). it can be packaged in a thermally enhanced so-8 ic package (where the drain leads are thermally connected to the leadframe under the die, or similar approaches), or even in more conventional power packages (d-pak). if the fets are surface mounted to the pcb, with only the area of the power planes to conduct the heat away, then the maximum load current will be limited by th e thermal ratings under those conditions. using conventional heatsinks or sufficient airflow can extend the limit of dissipation. fets can be paralleled for higher currents; this spreads the heat between the fets, which helps keep the temperature lower. however, the gate driver is now driving twice the gate capacitance, so there will be more dissipation in the ISL6534 gate drivers. typical values for maximum current (based on 8-pin soic fets surface-mounted on pcb, with no heatsinks or airflow) are 5a for a dual fet; 10a for single fets for upper and lower; and 20a for two fets in parallel for both upper and lower. these are just rough numbers; many factors affect it, such as pcb board area available for heatsinking planes, how close other dissipative devices are, etc. in general (and especially for short ugate duty cycles, such as converting 12v input down to 1v or 2v outputs), the upper fet should be chosen to minimize the gate charge, since switching losses dominate. since the lower fet is on most of the time, low r ds(on) should be the main consideration. the ISL6534 requires 2 n-channel power mosfets for each switcher outp ut. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. the following are some additional guidelines. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty factor (see the equations below). only the upper mosfet has switching losses, since the fet body diode (or optional external schottky rectifier) clamps the switching node before the synchronous rectifier turns on. f z1 1 2 r ? 2c1 ? ---------------------------------- = f z2 1 2 r1 r3 + () c3 ? ? ----------------------------------------------------- - = f p1 1 2 r2 ? c1 c2 ? c1 c2 + ---------------------- ?? ?? ? ------------------------------------------------------ - = f p2 = 1 2 r3 c3 ? ? ---------------------------------- 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensation gain (db) frequency (hz) gain 20log (v in / ? v osc ) modulator gain 20log (r2/r1) closed loop gain figure 16. asymptotic bode plot of converter gain p upper = i o 2 x r ds(on) x d + 1 2 io x v in x t sw x fs p lower = i o 2 x r ds(on) x (1 - d) where: d is the duty cycle = v o /v in , t sw is the switching interval, and fs is the switching frequency. ISL6534
19 fn9134.1 these equations assume linear voltage-current transitions and do not adequately model power loss due the reverse- recovery of the lower mosfets body diode. the gate-charge losses are dissipat ed by the ISL6534 and don't heat the mosfets. however, large gate-charge increases the switching interval, t sw which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. standard-gate mosfets (typic ally 30v breakdown and 20v maximum gate voltage) are normally recommended for use with the ISL6534, especially since 12v is expected to be available to drive the gates. however, logic-level gate mosfets can be used under special circumstances. the input voltage, upper gate drive level, and the mosfets absolute gate-to-source voltag e rating determine whether logic-level mosfets are appropriate. figure 17 shows the upper gate drive (boot pin) supplied by a bootstrap circuit from vcc12. the boot capacitor, c boot develops a floating supply voltage referenced to the phase node. this supply is refreshed each cycle to a voltage of vcc12 less the boot diode drop (v d ) when the lower mosfet, q2 turns on. a logic-level mosfet can only be used for q1 if the mosf ets absolute gate-to-source voltage rating exceeds the maximum voltage applied to vin = vcc12. note that a lower voltage supply (such as 5v) can also be used for bootstrapping, which would allow for a lower gate voltage rating; but only if the lower voltage is still high enough to turn the upper fet on hard enough. for q2, a logic-level mosfet can be used if its absolute gate-to- source voltage rating exceeds the maximum voltage applied to vcc12. figure 18 shows the upper gate drive supplied by a direct connection to vcc12. this option should only be used in converter systems where the main input voltage is +5 vdc or less. the peak upper gate-to-source voltage is approximately vcc12 less the input supply. for +5v main power and +12 vdc for the vin bias, the gate-to-source voltage of q1 is 7v. a logic-level mosfet may be a good choice for q1 (again, check the max gate voltage ratings) and a logic-level mosfet can be used for q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to vcc12. bootstrap trade-offs note again that bootstrapping to 12v requires that the upper fet have a maximum gate-source rating of greater than 12v. since the lgate output is sourced from the vcc12 supply in all cases, the lower fet must also have the high rating. so this may rule out using some 20v breakdown fets that have gate ratings of 12v or less. figure 17 shows the diode d boot and bootstrap capacitor c boot . a small capacitor (~1f; not shown) is sometimes used as a local decoupling cap; it should be placed near the anode of the diode to gnd. the anode of the diode is shown tied to vcc12, but it can also connect to vcc (even in the shunt regulator mode) or to vin or to another appropriate supply. figure 18 shows the direct hookup; the advantage is that two components (d boot and c boot ) are not needed; a possible disadvantage is th at the vcc12 may not be the optimum voltage for efficiency (perhaps a bootstrap diode/capacitor to 5v would be better, for example). once again, a small capacitor (not shown) located near the boot1 pin is sometimes used for decoupling. +12v pgnd ISL6534 gnd lgate ugate phase boot vcc12 +5v or +12v figure 17. upper gate drive - bootstrap option note: v g-s v cc12 - v d note: v g-s vcc12 c boot d boot q1 q2 d2 (optional) + - v d + - vcc12 (channel 1 or 2) pgnd +12v pgnd lgate ugate phase boot vcc12 +5v or less figure 18. upper gate drive - direct vcc12 drive option note: v g-s v cc12 - 5v note: v g-s vcc12 q1 q2 vcc12 d2 (optional) ISL6534 gnd + - pgnd (channel 1 or 2) ISL6534
20 fn9134.1 note that the phase node is not brought into the ISL6534, so there is no way to reference the gate voltage to it, as is often done in other regulators. the considerations for the boot2 pin are identical to boot1; but since they may have different vin, vout, fets, etc., the preferred solution for each output may be different for any given system. the voltage required on v boot (bootstrap voltage; the diode anode) depends primarily on the upper nfet r ds(on) and vth. a high voltage makes the r ds(on) as low as possible, which should help the overall efficiency; however, the high voltage makes the switching power in the gate driver higher, which lowers the efficiency. so the net overall effect is a trade-off between the two. at the other extreme, the voltage must be at least as high as the fet threshold voltage, plus a few volts of overdrive, in order to turn on the nfet hard enough to source the maximum load current. so the r ds(on) is not as low, hurting the efficiency, but the gate driver power is lower, which helps the efficiency. since the gate driver power is a function of (voltage) 2 , the theoretical optimum v boot voltage is to make it only high enough to turn on the nfet to handle the maximum load. however, since there are usually only a few available power supplies to choose from, the us er often must compromise. and sometimes the only supply available is the same one used for vin, which may be good for one term, but not as good for the other. the size of the bootstrap capacitor can be chosen by using the following equations: the last equation plugs in some typical values: n = 1; q g is 33nc, vin is 12v, v gs is 11v, ? v max = 1v. in this example, c boot 0.051f. this value is often rounded up to 0.1f as a starting value. note that bootstrap capacitors usually need to be rated at 16v, to handle the typical 12v boot. note that in general, as the number of fets or the size of the fets increases (which usually makes q g larger) or if vin or the bootstrap supply (if not vin) increases (for example, from 5v to 12v), these all require that c boot become larger. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient (and usually increases the dcr of the inductor, which decreases the efficiency). increasing the switching frequency (fs) for a given inductor also reduces the ripple current and voltage. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the ISL6534 will provide either 0% or 87.5% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current level. during this interval the difference between the inducto r current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. with a +5v input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. output capacitors selection an output capacitor is required to filter the ou tput and supply the load transient current. the filtering requirements are a function of the switching fr equency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are gener ally met with a mix of capacitors and careful layout. modern microprocessors produce transient load rates above 1a/ns. high frequency capacitors initially supply the transient c boot q gate ? v ------------------- - q gate nq g vin ? ? v gs ----------------------------------- = c boot q gate ? v ------------------- - nq g vin ? ? v gs ? v ? ----------------------------------- 13312 ? ? 11 0.7 ? --------------------------- - 0.051 f = = = where n is the number of upper fets q g is the total gate charge per upper fet vin is the input voltage v gs is the gate-source voltage (usually vin - diode drop) ? v is the change in boot voltage before and immediately after the transfer of charge; typically 0.7v to 1.0v and ? v out = ? i x esr ? i = v in - v out fs x l ------------------------------- - v out v in --------------- - ? t fall l o i tran v out ------------------------------ - = t rise l o i tran v in v out ? ------------------------------- - = ISL6534
21 fn9134.1 and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor val ues are generally determined by the esr (effective series resistance) and voltage rating requirements rather than act ual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulne ss of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. and keep in mind that not all applications have the same requirements; some may need many ceramic capacitors in parallel; others may need only one. use only specialized low- esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrol ytic capacitor's esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors incr eases with case size and can reduce the usefulness of the c apacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q1 turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of q1 and the source of q2. the important parameter s for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 ti mes greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. for both through-hole and surface-mount design, several electrolytic capacitors (panas onic hfq series or nichicon pl series or sanyo mv-gx or equivalent) may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. the tps series available from avx, and the 593d series from sprague are both surge current tested. snubbers a snubber network is a series resistor and capacitor, usually from the phase node to gnd (across the lower fet); it is used to dampen the ringing of the phase node, which can introduce noise into other parts of the circuit. in particular, jitter on the gate drivers can be caused by disturbances that trigger the programmable duty cycle edge of the internal ramp generator. if noise or ringing is a problem in your particular circuit, consider adding a snubber. typical values are 2.2nf for the capacitor, and 2.2 ? for the resistor. note that the resistor may have large currents, so use a 1/2w type resistor. the order of r and c doesn?t usually matter, but one preference is putting the resist or to gnd, such that the voltage across it can be easily measured on an oscilloscope to represent the current. see figure 19. optional schottky selection an optional rectifier d2 (see fig 17 or 18) is a clamp that catches the negative inductor swing during the dead time between turning off the lower mosfet and turning on the upper mosfet. the diode must be a schottky type to prevent the lossy parasitic mosfet body diode from conducting. if used, connect the cathode to the phase node, and the anode to pgnd. it is acceptable to omit the diode and let the body diode of the lower mosfet clamp the negative inductor swing, but efficiency will drop one or two percent as a result. the diode's rated reverse breakdown voltage must be greater than the maximum input voltage. margining and ?fine-tuning? margining can be added externally to a voltage regulator, in order to raise and/or lower the output voltage a nominal amount, such as 10%. the purpose might be to run the processor at higher voltage for faster clock speeds, or to run at lower voltages, to save power, for example. a straightforward method involves adding two extra resistors and two small fets (and re-adjusting r2, depending upon the decoding used); see figure 20. both resistors (rm1, rm2) are high values (10-100k ? ) compared to r1 and r2 (~1k ? ). so when placed in parallel with r2, it lowers the resistance of r2; pick the values for the desired amount. some simple logic is needed on the gates a and b to control them; pull-up or pull-down resistors might also be needed. figure 19. snubber component selection vin1 ugate1 lgate1 vout1 rsn1 csn1 phase1 ISL6534
22 fn9134.1 only 3 of the 4 possible states are shown decoded. there are other variations of this technique, but this shows the basic principle. since the fb are sensitive nodes, care should be taken in the layout, to keep the extra resistors near the pin. a variation of this technique can be used without the margining to fine tune the output voltage, when two 1% resistors (r1, r2) can?t give the exact value desired, and an active factory trim is not feasible. simply use a much higher value resistor in parallel with either r1 or r2 (or both) to fine-tune the value; a 100-1 ratio in resistor values will be able to change the voltage by roughly 1%; that might be good enough. short-circuit protection the ISL6534 does not have the typical over-current protection used by many of t he core processor ic?s. instead, it has a simple and inexpensive method of protection. but it is important for the user to understand the method used, and the limitations of that method. there are no sense pins available on the ISL6534. this means that the many standard ways of sensing output current (sense resistors, fet r ds(on) , inductor dcr, etc.) are not possible, without adding a lot of external components. there are also no phase pins available. monitoring under-voltage (by sensing drops on the fb pins, or on the outputs) was not done. the only method of protecti on for the two switching regulators is to monitor the comp1 and comp2 pins for over-voltage (and note that the linear output has no protection at all). what happens on a short-to-gnd on the output? as the output voltage is dragged down, the fb pin should start to follow, since it is usually just a resistor divider from the output. the loop detect s that the fb pin is lower than the error-amp reference, and the comp voltage will rise to try to equalize them; that will increase the duty-cycle of the upper fet gate driver (which allows more time to pull the output voltage higher). if the short is hard enough, the comp pin will rise higher and the duty cycle will increase further. if the short is still to o hard, at some point the comp pin output will go out of range, the duty cycle will hit the maximum, and the loop can no longer effectively try any harder. this is the point at which an over-current condition is detected. a comparator m onitors the comp pins, and if either one exceeds the trip point (nominal 3.3v), and stays above it for a filter time (1-2 clock pulses of the internal oscillator; 3-6s at the nominal 300khz; 2-4s at 500khz), then it will shut down both switchers, as well as the linear regulator, and require a por on either (or both) of the vcc12 or vcc power pins. there is no ?hiccup? mode, where it keeps trying. so that is the detection method; what are the implications of it? on the plus side, it?s built in, and the user doesn?t have to set anything to use it; no additional components are required. on the negative side, it is not easy to predict its performance, since many factors can affect how well it works. it was designed to detect a ?hard? short; like a screwdriver shorting the output to gnd. but defining how close to ?zero ohms? the short has to be in order to work properly is not straightforward. if the resistance is too high to trip the detector, the regulator w ill react simply as if the load has increased, and will continue to try to regulate up until the fets overheat. if the comp pi n doesn?t immediately rise to its trip point when the short is applied, chances are it won?t trip later as the fets heat up. so most of the potential problems can occur if the initial trip is missed. following are a list of the many possible factors that affect the performance: 1. if the power supply used for the vin of one of the regulators is shared with the vcc12 (or vcc) supply of the ic, then shorting t he output could potentially momentarily drag down the supply low enough to trip the vcc12 (or vcc) falling por, which could result in unpredictable behavior once the outputs shut off due to the por, and then try to start up into the short after the supply recovers. this scenario can be avoided with a ?stiff? power supply, or a separate one. 2. if the power supply for vin has a built-in current shutdown or limit, then it might shut-down before the ic, or the limiting might help the ic shutdown, either of which is generally good. however, many supplies used in real systems don?t have this built in, or would require a much higher current short than this scenario would provide. 3. if the circuit survives the initial short but doesn?t shut down, the removal of the short can cause an inductive kick on the phase node, which can create an over-voltage condition on the boot pin, which can in the worst case damage the ic and/or the fets. 4. the resistance of the short itself is probably the most critical factor affecting the over-current shutdown performance. if the short is not low enough resistance, then the part will not shutdown, and the fets can overheat. note that the ?short? to the output also includes wiring, pcb traces, contact resistances, as well as all of the return paths. 5. the higher the output voltag e, the more current you will get out of a fixed-resistance s hort, and the more likely you figure 20. margining component selection vout1 comp1 fb1 r1 r2 rm1 rm2 ab rm1, rm2 >> r1, r2 a off, b off 10% high a off, b on nominal a on, b on 10% low ISL6534
23 fn9134.1 will get a clean shutdown; see also #6. in addition, the higher vout for a given vin will give a higher ugate duty cycle, and the average comp voltage is hi gher, so it doesn?t have as far to go to trip. 6. in general, the faster the ri se time of the output current during the short, the more current will be allowed on the initial peak, and the better chance the comp pin will have a sharp rise as well. a low resistance short (#4) and a higher output voltage (#5) both help. however, if the current ramps too fast, then a false trip is also possible (shutting down at a current level still within the expected load range). 7. the load current at the time of the short can affect the results; the response of a short can be different at no load versus full load. 8. the compensation components are chosen to stabilize the regulation loop; however, if they unnecessarily load the comp output, that could affect the trip point response. 9. the output capacitance and its esr can affect how quickly the current ramps up during a short. 10. other variables that may contribute to a lesser degree include variations in the comp comparator and filter, the inductor l and dcr, the r ds(on) of the fet, the fb resistor dividers, the error amp reference voltage, the oscillator frequency, switching noise, vcc voltage, ambient temperature and airflow, and the layout of the pcb. 11. adding external circuitry to sense a fault may be possible, but subject to the usual limitations of those circuits. for example, sensing the output or fb voltage doesn?t always directly correlate with output current. so the recommendations are as follows: 1. if there is a specific fault condition that needs protection, try it out first under controlled conditions, either on an eval board, the final circuit, or something close to it, along with the power supply that will also be used. monitor vcc12 and vcc (to be sure they aren?t tripping por), the output and the co mp pin. a current probe monitoring the output current is also very useful. 2. compare the short circuit resistance to the nominal load resistance; if they are too close, the circuit may not work well. calculate how long the fets can sit at the higher current. is the short more likely from zero load or full load? 3. check the rise time of the short circuit current, and what happens if when the short is released. 4. from the waveform of the comp pin, see if the values can be optimized for the short condition. within the constraints of the stability criteria, smaller caps (in general) may give a quicker response. 5. note that the linear output has no protection at all. pcb layout considerations general layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or single point grounding. figure 21 shows the critical power components of the converter, for either output channel. to minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. the components shown in figure 21 should be located as close together as po ssible. please note that the capacitors c in and c o each represent numerous physical capacitors. locate the ISL6534 within 1-2 inches (or even less, if possible) of the mosf ets, q1 and q2. the circuit traces for the mosfets? gate and source connections from the ISL6534 must be sized to handle up to 1.5a peak current. figure 22 shows the circuit traces that require additional layout consideration. use single point and ground plane construction for the circuits shown. minimize any leakage current paths on each of the ss pins and locate the capacitors, c ss close to the ss pin because the internal current source is only 30 a. provide local v cc12 decoupling between vcc12 and pgnd pins, as well as the vcc and gnd pins. locate the capacitor, c boot as close as practical to the boot pin and phase node . note that the pgnd pins are used only for the gate driv ers and other output circuitry (including the vcc12 decoupling capacitor); the gnd pins are used by the vcc pin, and the control circuitry. they should be joined at a common point. pgnd l o c o lgate ugate q1 q2 figure 21. printed circuit board power and ground planes or islands v in v out return ISL6534 c in load ISL6534
24 fn9134.1 layout considerations for the ISL6534 the metal plate on the bottom of either the tssop or qfn (mlfp) package must be soldered down to the pc board, and sufficient plane area given for heat transfer. the plane should be connected to gnd (pin 15 in tssop); but if it is left floating, it should not be tied to any other potential. thermal vias are recommended to connect to a plane on the opposite side of the pcb, and to the internal gnd plane, for additional heat transfer. decoupling capacitors should be very close to the vcc12 and vcc5 pins, with vias to the gnd plane. the traces from the gate driv ers to the fets (ug1, ug2, lg1, lg2, drive3) should be shor t (for low resistance) and wide (to handle large currents); the pin spacing will limit the widths right near the package. but note that the closer the fets are to the ic, the more they will heat each other, so keep that thermal consideration in mind. boot1/2 capacitors should be near their pins; the bottom to phase and diode can be a little further away. if a separate small capacitor is used for the bootstrap supply (if different than either vin or vcc12), it should be located next to the bootstrap diode anode. other traces to keep short include: fb1/2/3: the resistor dividers should be near the ic; via to gnd plane; the signal from the vout can travel, since it is low impedance. resistor dividers used for references (from vref or vout or to refin) should be near the refin input. comp1/2: the compensation components should be close to these pins (as well as fb1/2 pins), with vias to the gnd plane. en_ss capacitors should be near pin, with vias to gnd plane. fs_sync resistor (if needed) should be near pin, with a via to gnd. output capacitors should be close to the loads, where the filtering will help most; small ceramic capacitors (~1f) in parallel help for high frequency transients. input capacitors should be near the vin pins of the fets; the input capacitor gnds should be close to the lower fet gnd as well. the vin plane should be large to heatsink the upper fet effectively, since the drain pin is usually the thermal node. by the same reasoning then, the phase node plane should also be large, since the lower fet drain is connected there. however, the phase node plane couples high frequency switching noise to other levels nearby, so it should be minimized for that reason. and don?t route any sensitive or high impedance signals over the phase planes. several placement approaches are possible: ic and output fets, caps, and inductors on top level; most of the miscellaneous resistors and capacitors on the bottom level; all components on top leve l, with output components facing pins 13-24 side of ic, and input components facing pins 1-12. +12v ISL6534 ss gnd vcc12 boot d1 l o c o v out load q1 q2 phase +v in c boot c vcc12 c ss pgnd vcc gnd c vcc figure 22. printed circuit board small signal layout guidelines ISL6534
25 fn9134.1 ISL6534 quad flat no-lead plastic package (qfn) micro lead frame plast ic package (mlfp) l32.5x5 32 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-2 issue c symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7,8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n322 nd 8 3 ne 8 8 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
26 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9134.1 ISL6534 thin shrink small outl ine exposed pad plastic packages (eptssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 0.05(0.002) top view p1 123 p bottom view n m24.173b 24 lead thin shrink small outline exposed pad plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.000 0.006 0.00 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.303 0.311 7.70 7.90 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n24 247 0 o 8 o 0 o 8 o - p - 0.197 - 5.00 11 p1 -0.126-3.2011 rev. 1 11/03 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-adt, issue f. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are s hown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. (angles in degrees) 11. dimensions ?p? and ?p1? are t hermal and/or electrical enhanced variations. values shown are maximum size of exposed pad within lead count and body size.

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